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  Break the Billion Gate barrier - How to overcome SOC design complexity
Time Room 1 - IC Room 2 - IC Room 3 - IC Room 4 - FV/ESL
8:00-9:00 Vendor Fair and Registration 
9:00-9:05 Welcome Speech
9:05-9:55 Keynote: Organizing by Design - by Walden Rhines, Mentor CEO
9:55-10:45(BJ) Keynote: BJ(GLOBALFOUNDERIES): The engaging model between fabless companies and foundries is changing; design and manufacturing are no longer distinct development activities. -by Henry Law
9:55-10:45(SH) Keynote: SH(TSMC) :Sky is the limit – how “going vertical” propels us into life of the future-by Cliff Hou
10:45-11:15 Vendor Fair & Cafe Break
SUB THEME Are you ready for the 20nm design challenges? 3DIC, the alternative approach to catch up with the growing design complexity and capacity Methodology for more robust designs: DFM driven P&R and DFT solutions From simulation to emulation, how to speed up your SOC verification?
11:15-12:00 1.1: Advanced Filling Techniques for N20 and Beyond with SmartFill (GLOBALFOUNDRIES & Mentor) 2.1: Advanced Physical Verification and Extraction for 20nm and 3DIC (SH) (TSMC & Mentor)
2.1 Advanced Physical Verification for 20nm and 3DIC (BJ)
3.1: Olympus-SoC: Addressing 20nm Place and Route Challenges 4.1: The Questa Static Verification Solution: 5 Easy Ways to Adopt Ultra-high Performance Formal Tools
12:00-13:15 Vendor Fair & Lunch Break
13:15-14:00 1.2: Advances in DFM at SMIC (SMIC & Mentor) 2.2: Advances in 3DIC Technologies (SH)
2.2: Advanced Extraction for 20nm and 3DIC (BJ)
3.2: Tessent Shell: New Flexible Integrated Test Platform 4.2: The Questa Platform: Generating Coverage Models and Achieving Coverage Closure
14:00-14:45 1.3: After Tapeout, Now What? (SMIC) 2.3:Overcome Time-to-Market bottlenecks for Custom Design Process 3.3: Tessent Support of ARM Cores and Memories (ARM & Mentor) 4.3: Next Generation Emulation Solutions
14:45-15:05 Vendor Fair & Coffee Break
15:05-15:50 1.4: Using Calibre PERC for ESD protection and Comprehensive Circuit Reliability Verification (SMIC & Mentor) 2.4: ​ New Large Scale Simulation & Verification Solutions 3.4: Accelerating Yield Ramp with Diagnosis and DFM Analysis (Freescale & Mentor) 4.4: Calypto Low Power RTL and ESL Solution
4.5: Next Generation Emulation Solutions
15:50-16:20 Closing, lucky draw

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