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  Mentor Forum 2015 亚太区设计技术论坛(北京)
Time AM: Track 1 - Calibre and P&R AM: Track 2 - Functional Verification
9:00 - 9:40 Registration / Welcome Coffee / Vendor Fair
9:40 - 10:20 1.1 Calibre Overall Solutions for Advanced Nodes
Lingyun Zhang
2.1 Enterprise Verification: Productivity from Formal - Simulation - Emulation
Yuxin You
10:20 - 11:00 1.2 Fill-as-you-go: New way to cut your 16nm design verification run time
WeIQing Liu
Zhuihua Zhou/HiSilicon
2.2 Creating a VirtuaLAB - Increase Your SoC Verification Productivity (Veloce)
Ricky Yang
11:00 - 11:40 1.3 Competing in Reliability Focused Growth Markets with Calibre PERC
Lingyun Zhang
2.3 EZ Design and Verification of AMBA® Based Designs (ARM)
Yuxin You & Jason Zhao/ARM
11:40 - 13:00 Lunch / Vendor Fair
START - END PM: Track 1 - Calibre and P&R PM: Track 3 - DFT and AMS
13:00 - 13:40 1.4 calibre Multi Patterning update: Mandatory for 20nm design and advanced
Vincent Ni
3.1 Saving time and cost of your FinFET designs through truly integrated hierarchical DFT solution
Fanjin Meng
13:40 - 14:20 1.5 calibre XACT/xRC update: parasitic extraction for advanced nodes/advanced designs
Li Li
3.2 Accurate nm Circuit Verification and Device Noise Analysis of Analog / Mixed-Signal ICs
Quan Ma
14:20 - 14:40 Coffee Break
START - END PM: Track 1 - Calibre and P&R PM: Track 4 - PCB
14:40 - 15:20 1.6 calibre DESIGNrev/RealTime update: efficient Chip Tapeout Preparation/verification solution
Weiqing Liu
4.1 Optimized Co-design of an IC / Package / PCB System
Julian Sun
15:20 - 16:00 1.7 Oasys R.TD
Chen Geng
4.2 Accurate Electromagnetic Modeling of IC Packages and how to optimize Systems Performance with Electrical Sign-off
Lifu You
16:00 - 16:10 Closing Comment / Lucky Draw

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